1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly relates to a technique of highly integrating a semiconductor memory device.
2. Description of the Background Art
Conventionally, there have been proposed layout structures of an SRAM (Static Random Access Memory) for high integration (e.g. see Japanese Patent Laying-Open No. 09-270468 and Japanese Patent Laying-Open No. 10-178110). An SRAM cell in these documents consists of six transistors, and thus due to variations among the transistors associated with miniaturization, data may be written to the memory cell at the time of readout via a bit line precharged to a high level, so that stable readout may not be performed.
In contrast, there is disclosed a 2-port SRAM cell consisting of eight transistors (e.g. see Japanese Patent Laying-Open No. 2002-237539 and Japanese Patent Laying-Open No. 2002-043441).
Although the SRAM cell in Japanese Patent Laying-Open No. 2002-237539 and Japanese Patent Laying-Open No. 2002-043441 is highly integrated to a certain degree, a sufficient level of integration has not yet been reached. The SRAM is not highly integrated particularly in a direction of the columns, so that the length of bit lines is still large, and that data readout from the memory cell and data write to the memory cell are performed at a low speed and require high power. Further, the SRAM cell consisting of eight transistors described in Japanese Patent Laying-Open No. 2002-237539 and Japanese Patent Laying-Open No. 2002-043441 has not yet achieved sufficient stability of the readout.